Parallel speed-up and efficiency in single loop sums and matrix multiplication

Authors

  • Robert C. Tacbad National Institute of Physics, University of the Philippines Diliman
  • Francis N. C. Paraan National Institute of Physics, University of the Philippines Diliman

Abstract

This study aims to evaluate the performance of parallel implementations of single loop sums and matrix multiplication using the Message Passing Interface. Benchmark results were obtained from the available computing resources of the Structure and Dynamics Group (SanD). These implementations were run using 1 to 24 processors and their speed-up and efficiency were calculated. Nearly ideal speed up and efficiency was observed when tasks were distributed over physical cores of a single CPU.

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Issue

Article ID

SPP2013-PB-9

Section

Poster Session PB

Published

2013-10-23

How to Cite

[1]
RC Tacbad and FNC Paraan, Parallel speed-up and efficiency in single loop sums and matrix multiplication, Proceedings of the Samahang Pisika ng Pilipinas 31, SPP2013-PB-9 (2013). URL: https://proceedings.spp-online.org/article/view/SPP2013-PB-9.