Hysteresis and p-n junction capacitance investigations of DE MOSFET

Authors

Gilbert Gubatan ⋅ PH National Institute of Physics, University of the Philippines Diliman
Maria Michiko Alcanzare ⋅ PH National Institute of Physics, University of the Philippines Diliman
Ed Adrian Dilla ⋅ PH National Institute of Physics, University of the Philippines Diliman
Neil Irvin Cabello ⋅ PH National Institute of Physics, University of the Philippines Diliman
Alva Presbitero ⋅ PH National Institute of Physics, University of the Philippines Diliman
Rommel Paulo Viloan ⋅ PH National Institute of Physics, University of the Philippines Diliman
Vernon Julius Cemine ⋅ PH Perkin Elmer Optoelectronics Philippines, Inc.

Abstract

In this study, the hysteretic behavior and the p-n junction capacitance of an IRF530 metal-oxide-semiconductor field-effect transistor (MOSFET) were investigated utilizing an actual basic circuit setup. Hysteresis was more evident at high voltage frequencies. Moreover, it was monitored to approach higher threshold input frequency for negative offset voltage than without the offset. The behavior is accounted to the non-instantaneous response of the charge carriers within the depletion region of the p-n junction between transistor’s drain and source. It was also observed that junction capacitance decreases for higher offset voltage values and as the voltage frequency increases. The resulting trend agreed with the theoretical relations.

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Issue

2009: Proceedings of the 27th Samahang Pisika ng Pilipinas Physics Congress

Article ID

SPP-2009-PA-15

Section

Poster Session PA

Published

2009-10-28

How to Cite

[1]

G Gubatan, MM Alcanzare, EA Dilla, NI Cabello, A Presbitero, RP Viloan, and VJ Cemine, Hysteresis and p-n junction capacitance investigations of DE MOSFET, Proceedings of the Samahang Pisika ng Pilipinas 27, SPP-2009-PA-15 (2009). URL: https://proceedings.spp-online.org/article/view/SPP-2009-PA-15.