Nonvisible defect characterization using scanning capacitance microscopy

Authors

Alvarado B. Tarun ⋅ PH Quality and Reliability Department, Intel Technology Philippines, Inc.
Jean N. Laniog ⋅ PH Quality and Reliability Department, Intel Technology Philippines, Inc.
Jonah Tan ⋅ PH Quality and Reliability Department, Intel Technology Philippines, Inc.
Proceso Cana ⋅ PH Quality and Reliability Department, Intel Technology Philippines, Inc.

Abstract

We develop a technique to study junction leakage in an advanced complementary metal oxide semiconductor (CMOS) device using Scanning Capacitance Microscopy (SCM). Progressive metal cuts and direct probing were performed to isolate the affected test structure. A reverse bias voltage was applied across the n-well and p-type diffusion layer. The current-voltage (I-V) curves obtained confirmed presence of leakage in the test structures. The SCM data revealed that the marginal leakage current is due to higher n-well doping level of the device compared to the control. Furthermore, the diode-tunneling equation was simulated and the results are in good agreement with empirical data. The SCM technique can therefore be very useful for defect localization and physical failure analysis in samples without interconnects or electrodes to aid in root cause identification.

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Issue

2002: Proceedings of the 20th Samahang Pisika ng Pilipinas Physics Congress

Article ID

SPP-2002-2C-06

Section

Instrumentation and Optics

Published

2002-10-23

How to Cite

[1]

AB Tarun, JN Laniog, J Tan, and P Cana, Nonvisible defect characterization using scanning capacitance microscopy, Proceedings of the Samahang Pisika ng Pilipinas 20, SPP-2002-2C-06 (2002). URL: https://proceedings.spp-online.org/article/view/SPP-2002-2C-06.