Finite element analysis in optimizing leadframe design for the 4-Leaded SOT223 VHVIC Device

Abstract

The drive to miniaturize the Very High Voltage Integrated Circuit (VHVIC) device has lead to the use of a 4-Leaded SOT223 package. This miniaturized package solution must withstand the electrical and thermal requirements of 700V and 5W, respectively, as well as the assembly mechanical loads. Internal geometric design of an IC package plays a crucial part in its overall integrity. As a design consideration, the internal metal portion of the package carrier – the leadframe (LF), was maximized to readily address the thermal resistance. The viability of these considerations must be carefully evaluated in every assembly process step.
Gross LF backside delamination (LFBD) was observed to occur at the forming process during the initial run of the new leadframe design as inspected on C-SAM. Direct correlation of actual assembly response, C-SAM and finite element analysis is done which leads to optimize LF design that can withstand LFBD.
Stress distributions in the interface of the LF and LF's bottom mold layers are used to understand the mechanism of the LFBD. Given the two-dimensional contour map of the two layers, the contrasting direction of stresses in the z-axis, the axis perpendicular to the LF plane, reveals the reason why the interface tends to delaminate. This scenario is seen at leadframe neck portion, between the heatsink and the die flag, as evidently manifested by the actual initial engineering run.